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A comment on Show HN: A pipelined RISC-V processor written in VHDL. Parent comment

Re:Show HN: A pipelined RISC-V processor written in VHDL by gluggymug on Wednesday July 29, 2015 @03:28PM (#9971020)
I saw a little info on that at https://github.com/ucb-bar/fpga-zynq

I guess you are referring to that?

It's supposed to be a relatively mature tool so there's got to be a version that works ok.

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