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A comment on Show HN: A pipelined RISC-V processor written in VHDL. Parent comment

Re:Show HN: A pipelined RISC-V processor written in VHDL by _chris_ on Tuesday July 28, 2015 @06:24PM (#9964964)
Then please submit an issue to the github issue queue. Don't complain on some internet forum and hope that somebody will read your mind. It works fine for me.
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Re:Show HN: A pipelined RISC-V processor written in VHDL by rjsw on Tuesday July 28, 2015 @06:39PM (#9965042)
I don't have a github account.

I just suggested a reason why someone might choose to use a conventional HDL.

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Re:Show HN: A pipelined RISC-V processor written in VHDL by _chris_ on Tuesday July 28, 2015 @07:21PM (#9965205)
Sure, I don't mean to suggest there aren't valid reasons for writing cores in VHDL, etc., I just want to clarify that Chisel (unlike say Verilog) will, by fiat, only ever generate synthesizable code. If that's ever not the case, you should let them know.
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