Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by p1esk on Thursday June 18, 2015 @09:48PM (#9742643)

+1 for Verilog. SystemVerilog is the way to go.

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Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by krapht on Thursday June 18, 2015 @09:52PM (#9742657)

I like VHDL. Verilog and non-blocking vs blocking assignments can trip you up so easily. As for verbose code, you spend way more time debugging and thinking about how to structure a program than you do writing text on the screen.

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Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by blackguardx on Thursday June 18, 2015 @11:00PM (#9742789)

I prefer Verilog but what you say is true or at least should be true if you want to end up with a good, easily debuggable result.

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Re:Designing a CPU in VHDL, Part 1: Rationale, Tools, Method by mng2 on Thursday June 18, 2015 @11:42PM (#9742905)

I like VHDL, but SystemVerilog does have some very nice features.

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