Re:Using voltage glitching to unleash the A100 in my mining ...
by tintor on Wednesday November 11, 2026 @10:32AM
(#50454622)
When yields get better, manufacturer can just produce the lower tier chip directly.
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Re:Using voltage glitching to unleash the A100 in my mining ...
by WarmWash on Wednesday November 11, 2026 @10:41AM
(#50454719)
They still wouldn't because economies of scale make it cheapest to only build one model.
Re:Using voltage glitching to unleash the A100 in my mining ...
by bethekidyouwant on Wednesday November 11, 2026 @11:02AM
(#50454967)
Its not economies of scale. Why or how would you even etch a worse pattern on the same fabrication node? They don’t even have a mask for the worse version its literally just the same pattern with more defects.
Re:Using voltage glitching to unleash the A100 in my mining ...
by WarmWash on Wednesday November 11, 2026 @11:44AM
(#50455460)
They only make one design because of economies of scale. I think there might have been some confusion here
Re:Using voltage glitching to unleash the A100 in my mining ...
by cowlevel on Wednesday November 11, 2026 @04:48PM
(#50459163)
Maybe you can get more of them per wafer because they're smaller?
Re:Using voltage glitching to unleash the A100 in my mining ...
by bethekidyouwant on Wednesday November 11, 2026 @06:48PM
(#50460709)
Yes but that’s a different thing those smaller chips also get binned based on defects
Re:Using voltage glitching to unleash the A100 in my mining ...
by tintor on Wednesday November 11, 2026 @05:37PM
(#50459789)
What economies of scale are you referring to?
Each wafer is printed separately. They don't build new custom production line for each new design.
Re:Using voltage glitching to unleash the A100 in my mining ...
by toast0 on Wednesday November 11, 2026 @11:10AM
(#50455055)
This wouldn't really work for AMD processors... They could design and fab a 6-core chiplet, but it would need to be the same size as the 8-core chiplets so it would interface to the same carriers. If the footprint is the same, the fab cost is roughly the same, so spending the design time on that doesn't make sense. If they build separate carriers, that's more design time and inventory management and it may well be more expensive than just building 8-cores and disabling two.
That said, with Zen6 having 12 cores per chiplet, I wouldn't be surprised if they eventually end up designing a smaller chiplet with 6 cores and a dedicated small chiplet carrier. Or push 6 core SKUs to the APU side that doesn't use chiplets and I think has small core count variants.
Re:Using voltage glitching to unleash the A100 in my mining ...
by deaton on Wednesday November 11, 2026 @01:49PM
(#50456977)
No, they can't. The lower tier chips exist pretty much entirely because they can be easily converted from the higher tier chips that are defective. Purpose-building a lower tier chip would be a ludicrously expensive thing to do, or else they'd already be doing that.
Re:Using voltage glitching to unleash the A100 in my mining ...
by LoganDark on Wednesday November 11, 2026 @04:22PM
(#50458882)
A fun example of this is Apple, who used to build three dies for each M-series generation (base, Pro, Max) but now build just two (base, Pro/Max). You'd think one of the most bespoke companies on the planet would not be moving to fewer dies unless there were very compelling reasons to do so.