I would imagine this is of decent interest to people reverse engineering chip designs, or doing failure analysis, so it’s possible someone might actually be trying this at scale.
Re:Every processor die anyone has photographed and given away
by Arubis on Saturday November 07, 2026 @06:01PM
(#50408870)
You can destructively deprocess dies, removing a layer at a time and imaging at each layer. 20ish years ago you could still do this with a polishing wheel and a fine slurry; don’t know if that’s still viable.
Re:Every processor die anyone has photographed and given away
by femto on Saturday November 07, 2026 @08:51PM
(#50409808)
I've got a copy of "High Tech: Window to the Future"
by Gene Bylinsky. It's got an actual Am8052 die embedded in the front cover. Published in 1986, so it is ancient, but it covers they heyday of microprocessor development, when transistors were big enough to see. It's not a "deep" boo, but it does have plenty of pretty pictures.
Re:Every processor die anyone has photographed and given away
by throwa356262 on Sunday November 08, 2026 @03:07AM
(#50411317)
I belive what we today see as x86 started with the 386, from 1985-ish. Not 8008 which is a completely different architecture and ISA.
Todays PCs run AMD x64, which some people call x86-6. But again this is a completely different beast from good opd x86. It was introduced in 2000 after Intels 64 architecture failed miserably.
Re:Every processor die anyone has photographed and given away
by adrian_b on Sunday November 08, 2026 @05:00AM
(#50411849)
Most instructions of 8008 are still implemented by the latest Intel-AMD CPUs, even if for most of them there is normally no reason to use them, especially in a 64-bit program, where operations with 8-bit registers should be avoided.
Re:Every processor die anyone has photographed and given away
by throwa356262 on Sunday November 08, 2026 @05:33AM
(#50412015)
Just because they can execute similar instructions it doesnt mean they are the ssame. 8008 came from a common-bus design with an accumulator-centric ISA, which is miles aways from today's x64 architecture.
Besides, ISA is just the CPU frontend and does not reflect the uarch. You can probably make a Ryzen execute ARM or MIPS code by changing a few frontend opcode / fw tables.
Re:Every processor die anyone has photographed and given away
by bajard on Sunday November 08, 2026 @08:35AM
(#50413228)
Insufficient support for operations with 8-bit registers is a bottleneck even in 64-bit CPUs.
For example, let's suppose that you have a for loop. You could update 8 uint8 values simultaneously by packing them into a uint64 and adding a constant. But when you need to unpack those 8 bytes to actually use them as indexes, the unpacking costs a lot of CPU cycles, so you lose the advantage you gained by avoiding 8 separate additions.
All you can do is access AH and AL (or `SIL`, `DIL`, `BPL`, `SPL`, etc.), but this does not take just 1 CPU cycle. It takes many cycles, and only the lowest bytes can be accessed. There is a lot of performance left on the table because of insufficient support for small registers inside larger registers.
Re:Every processor die anyone has photographed and given away
by AlAjem on Sunday November 08, 2026 @03:52AM
(#50411513)
With the early dies with thousands of transistors you really can see the logic gates, once it gets to the millions you can see the structures minimized and multiplied but once it gets to the billions on modern dies it becomes so small and abstract I wonder if any image can capture the detail contained in them.
I would imagine this is of decent interest to people reverse engineering chip designs, or doing failure analysis, so it’s possible someone might actually be trying this at scale.
Garbage in, it’ Herpes.
https://openlibrary.org/works/OL6322148W/High_Tech?edition=k...
https://www.ebay.com.au/itm/334312859146
https://www.righto.com/
https://news.ycombinator.com/from?site=righto.com
Todays PCs run AMD x64, which some people call x86-6. But again this is a completely different beast from good opd x86. It was introduced in 2000 after Intels 64 architecture failed miserably.
Besides, ISA is just the CPU frontend and does not reflect the uarch. You can probably make a Ryzen execute ARM or MIPS code by changing a few frontend opcode / fw tables.
For example, let's suppose that you have a for loop. You could update 8 uint8 values simultaneously by packing them into a uint64 and adding a constant. But when you need to unpack those 8 bytes to actually use them as indexes, the unpacking costs a lot of CPU cycles, so you lose the advantage you gained by avoiding 8 separate additions.
All you can do is access AH and AL (or `SIL`, `DIL`, `BPL`, `SPL`, etc.), but this does not take just 1 CPU cycle. It takes many cycles, and only the lowest bytes can be accessed. There is a lot of performance left on the table because of insufficient support for small registers inside larger registers.
But all the legacy operating modes too? A modern x86 cpu should only have 2:
# Full-on 64 bit, legacy cruft cleared out as much as possible
# A compatibility mode to run application code written for 32-bit protected mode OSes like Win2k/XP etc
And even that last mode could be optional. Any other legacy support is just waste of transistors imho (however 'few').
Intel made a move in that direction years ago. Sadly that went nowhere.
The site links to its original pictures which allow zooming in much further on a phone revealing more details.