Re:Every processor die anyone has photographed and given away
by bajard on Sunday November 08, 2026 @08:35AM
(#50413228)
Insufficient support for operations with 8-bit registers is a bottleneck even in 64-bit CPUs.
For example, let's suppose that you have a for loop. You could update 8 uint8 values simultaneously by packing them into a uint64 and adding a constant. But when you need to unpack those 8 bytes to actually use them as indexes, the unpacking costs a lot of CPU cycles, so you lose the advantage you gained by avoiding 8 separate additions.
All you can do is access AH and AL (or `SIL`, `DIL`, `BPL`, `SPL`, etc.), but this does not take just 1 CPU cycle. It takes many cycles, and only the lowest bytes can be accessed. There is a lot of performance left on the table because of insufficient support for small registers inside larger registers.
For example, let's suppose that you have a for loop. You could update 8 uint8 values simultaneously by packing them into a uint64 and adding a constant. But when you need to unpack those 8 bytes to actually use them as indexes, the unpacking costs a lot of CPU cycles, so you lose the advantage you gained by avoiding 8 separate additions.
All you can do is access AH and AL (or `SIL`, `DIL`, `BPL`, `SPL`, etc.), but this does not take just 1 CPU cycle. It takes many cycles, and only the lowest bytes can be accessed. There is a lot of performance left on the table because of insufficient support for small registers inside larger registers.