Just trying to understand.
What I mean is not all nets are created equal. Is this an edge sensitive gpio or a level sensistive? Is this a net with a cap a current that's being integrated or edge rate control on a clock driver? A person knows because they can read the datasheets. The way for the algorithm to know is routing constraints, and their fairly tedious to write correctly which means for there to be good ROI on the time spent writing them, the algorithm needs to do a lot of work for you.
Yeah, you've listed off ~100 nets vs 1000s+ nets. But...
Many MPUs are BGA200 to BGA400 in size, and seemingly designed for 4-layer to 6-layer boards (available from OSHPark). Which means I expect around... maybe 200 nets or so in practice (a lot of the pins are either power-or-ground. But many other pins would be in fact connected to "something" and be their own net). More than your first number, less than your second number.
In your opinion, is that still within the feasibility of a hobbyist laying things out by hand? A lot of SiP MPUs have "internal DDR2" in sufficient quantities to boot Linux, although I'm also thinking about routing my own RAM for maximum flexibility.
That why for commercial PCB packages with support designs with 1000s of nets, such as Cadence's Allegro, one does see support for automatic routing of PCBs. And it's quite good.