That why for commercial PCB packages with support designs with 1000s of nets, such as Cadence's Allegro, one does see support for automatic routing of PCBs. And it's quite good.
Just trying to understand.
What I mean is not all nets are created equal. Is this an edge sensitive gpio or a level sensistive? Is this a net with a cap a current that's being integrated or edge rate control on a clock driver? A person knows because they can read the datasheets. The way for the algorithm to know is routing constraints, and their fairly tedious to write correctly which means for there to be good ROI on the time spent writing them, the algorithm needs to do a lot of work for you.
Yeah, you've listed off ~100 nets vs 1000s+ nets. But...
Many MPUs are BGA200 to BGA400 in size, and seemingly designed for 4-layer to 6-layer boards (available from OSHPark). Which means I expect around... maybe 200 nets or so in practice (a lot of the pins are either power-or-ground. But many other pins would be in fact connected to "something" and be their own net). More than your first number, less than your second number.
In your opinion, is that still within the feasibility of a hobbyist laying things out by hand? A lot of SiP MPUs have "internal DDR2" in sufficient quantities to boot Linux, although I'm also thinking about routing my own RAM for maximum flexibility.
There is a huge difference between autorouting in VLSI and autorouting in PCBs. There are particular differences:
1) The number of available layers
VLSI autorouting pretty much sucked until you had 5+ layers. You pretty much need local, horizontal, vertical, global, and pad as a minimum and the more layers the better the autorouter gets. Note that this is already more layers than generally exist on most PCBs which are typically 4 layer (upper, gnd, power, lower).
2) Changing layers in VLSI is relatively cheap without obstacle while changing layers in PCB is expensive and creates obstacles.
Changing a layer in VLSI is generally a couple of vias and no big deal. The vias are typically smaller than the metal track (but not always) and generally only connect the two layers in question.
Changing a layer on a PCB is generally expensive. PCB vias are generally larger than the metal trace and generally penetrate the entire PCB creating an obstacle on all layers. Take a look at PCB boards for FPGAs: they are generally 8+ layers and use expensive blind vias for routing breakout. Those kinds of PCBs are relatively expensive, and even those don't lend themselves to autorouting that well.
3) A lesser difference is that for high-speed signals PCB physical dimensions can be on the order of magnitude of the size of the wavelength of the signal being transmitted while VLSI dimensions are typically much smaller.
For example, a quarter wavelength for 6GHz is roughly 1cm which is generally bigger than most chips and significantly smaller than most PCBs. The design considerations for VLSI autorouting generally can ignore differences in routing length or layer changes (but not always).
On the other hand PCBs often need to be length matched fairly carefully for things like RAM buses. They also sometimes need to account for the fact that PCB materials are inhomogeneous--your routing track has different electromagnetic properties depending upon whether it is over glass fiber or epoxy. Thus, your PC motherboard tends to be routed at odd angles like 7 or 10 degrees to average out the effect.
Because of all of this, PCB autorouters are HARD and the KiCad developers have (rightfully, IMO) decided that they're time is much better spent on the myriad other features and bugs rather than developing a PCB autorouter.
However, if I'm sure that if you were willing to take a crack at it, the KiCad developers would be ecstatic to give a pointer to your amazing autorouter. Just be prepared that it's going to be quite difficult and you're going to get LOTS of complaints about how much it sucks.
I look forward to seeing your efforts.