xw3099

This deck has a great introduction to mapping and the references at the end are more up to date

https://www.eng.biu.ac.il/temanad/files/2018/11/Lecture-4-Sy...

That book is really great if it’s your job to write timing constraints. If you’re interested in timing theory I think this is a bit better.

https://books.google.com/books/about/Timing.html?id=80gOBwAA...

It’s definitely doable in one off quantities. And in fact people do it. Probably the most annoying thing would be dealing with length matching but honestly modern interfaces are much more tolerant than the specs imply. Power delivery could also be a sore point. So again, if you just looking to get a prototype working, it’s workable. But in volume. I wouldn’t go this route. This presentation lists some important things that are lacking in KiCAD when you really need to know the answer. https://archive.fosdem.org/2022/schedule/event/advanced_sim/...

> surely no strategy that worked to launch a project from tiny seed to maturity and market saturation has ever then failed to keep it relevant in the long term...

If the rate of submissions falls then it certainly makes sense to adjust. Until then, don't fix what isn't broken.

It could definitely benefit. And if KiCAD wants to support larger systems then one might even argue they're required, eventually.

What I mean is not all nets are created equal. Is this an edge sensitive gpio or a level sensistive? Is this a net with a cap a current that's being integrated or edge rate control on a clock driver? A person knows because they can read the datasheets. The way for the algorithm to know is routing constraints, and their fairly tedious to write correctly which means for there to be good ROI on the time spent writing them, the algorithm needs to do a lot of work for you.

The barrier to automatic placement and route at the PCB level is not the algorithms. It the time it takes the user to create the routing constraints on the nets. For PCBs with less than, say, 100 nets. It's probably not worth it. You could wire it up manually faster than you could write and debug a constraints file.

That why for commercial PCB packages with support designs with 1000s of nets, such as Cadence's Allegro, one does see support for automatic routing of PCBs. And it's quite good.

That book is great. This one is also quite good.

https://books.google.com/books?id=EkPMBQAAQBAJ&printsec=fron...

Handbook of Algorithms for Physical Design Automation edited by Charles J. Alpert, Dinesh P. Mehta, Sachin

The information is available if one looks for it. It's a tough subject though.

> Maybe that's by design, but it doesn't feel sustainable in the long term.

That could be, but on the other hand, the Linux kernel is more than 30 years old and is on its 6th version...

One might also consider the rarity of maintainers who can write high quality code and donate large amounts of time. To find and retain someone like that one might also be required to allow them to be curt with random people on the internet from time to time. I can see how drive by contributions could get old fast from their point of view.