I don't see the departure?

AM4 cpus have an x16 for GPU, an x4 for NVMe storage, and an x4 for chipset, according to the article, AM5 cpus will have an x16 for GPU, an x4 for NVMe storage, and adds an x4 for for USB4 or more NVMe storage, and then an x4 for chipset, plus whatever the USB stuff means.

The rumored chipset takes that x4 and offers two x4s, four sata/3.0 x1 ports, and 6 usb3, six usb 2 ports.

There were a bunch of different chipsets for am4, most of which didn't have more connectivity than that. If you build the x670 link two of the new chipsets, and consider the added x4 from the cpu, you still have pretty similar connectivity as the x570, but you only have 12 lanes squeezing into the x4 for chipset instead of 16. There's certainly a discussion to be had about the CPU lanes being 5.0 and the chipset lanes (including uplink to the CPU, apparently) being 4.0; but while there's not much in the way of PCIe 5.0 devices, it's mostly hypothetical. If PCIe multiplexers weren't immensely expensive, the 24 CPU lanes at PCIe 5.0 would be equal to 48 lanes of PCIe 4.0 (plus 4 more for the chipset), and pretty close to the Zen2 Threadrippers's 56 + 8. Lack of cheap multiplexers means that's not really how the cookie crumbles though.

The three x4 links aren't sharing equally. One gets half bandwidth, two get a quarter each, when contended. If you're trying to read data off three drives, it's going to appear like one is twice as fast. But then you try to reproduce reading data off one drive at a time, and they all work at the same speed.

Ok, but if you had 5 x4 drives before, one got full bandwidth from the cpu x4, and the other four would share (equally, I guess) on the chipset x4. Now, you'd get two on the uncontended cpu x4 lanes, and the three sharing (unequally, as you mention), seems slightly better that last time, but not an 'unusual departure' from the previous design; the CPU to chipset link is still very oversubscribed, but now, you can add a second oversubscribed chipset if you want, instead of having a choice between chipsets with different levels of oversubscription (or no chipset, only available in boards that don't expose most of the lanes)

According to the article, there is no departure from their previous generation.

On the contrary, compared with the previous generation, the AM5 socket has more PCIe lanes, because it has 4 additional PCIe lanes, to attach directly to the CPU a Thunderbolt/USB4 controller, for maximum performance.

The changes are strictly in the chipset, which will now be able to provide more PCIe lanes than before, on more expensive motherboards with 2 southbridge chips, but with the price that the extra lanes will pass through an additional PCIe switch, so they will have a greater latency and their throughput can be diminished by congestion, when all the peripherals are active simultaneously.

Nevertheless, with 64 Gb/s links between chips (4 x PCIe 4.0), few peripherals will be fast enough to saturate the links and cause congestion, i.e. typically only the extra SSDs or extra GPUs, besides the primary GPU and the primary SSD, which are attached directly to the CPU.

So the extra SSDs and the extra GPUs should be preferentially attached to the first southbridge chip, not to the second. This is the change about which the users of the new AM5 motherboards must be aware.

Threadripper/HEDT is a different line, socket, and chipset. This is for the consumer stuff and looks to have the same number of CPU direct lanes as last generation, just higher speed.

I am aware and I believe I accurately described first these rumored changes to the Ryzen line, and second the rumored cutting of the consumer Threadripper line.

Is there some way I could edit my comment to make it clearer?

> This is for the consumer stuff and looks to have the same number of CPU direct lanes as last generation, just higher speed.

I think I disagree, as the PCIe4.0x4 slot off the chipset is now an additional step removed (& subject to greater contention). But I digress, my point is that AMD risks leaving a gap in their market coverage by doing two things:

1. There are rumors they are no longer competing in consumer-accessible high lane count CPUs/chipsets.

2. They have an opportunity with the next gen Ryzen to close the gap by (1.) offering more lanes at 4.0 speed (they could offer 40 CPU-attached lanes!) but by moving to 5.0 exclusively, they limit expansion options.

If both leaks/rumors are true, it suggests a missed opportunity.

I think it'd be a little clearer to avoid referring to any of the Threadripper family as "below HEDT" or the sort. That's the Ryzen 9 family, even the lowest end plain Threadripper was always HEDT. Nothing here has changed for the consumer market.

I won't comment much on the rumour side but overall I'm not as worried about whether things are named "Threadripper" vs "Threadripper PRO" as this never set the price floor anyways E.g. a 16 core Ryzen Threadripper PRO 3950X was $350 MSRP higher than a 16 core Ryzen 9 3950X.

Whether or not they ever release anymore low price high lane count options is an interesting question but that AM5 was supposed answer this and because it didn't AM5 is a departure from the past is just too many layers of assumption, rumour, and leaks to make any useful discussion about.

I think you're still misreading me. The first graf is largely about Ryzen, and their 16 core model is just below HEDT. If anything, that SKU raised the ceiling for mainstream/consumer parts well into the HEDT space except by lane count/expansion options.

Threadripper changed the definition of HEDT, but rumor is that there won't be a Zen 3/4 option for it, and those users will only have Intel as an option. That's the unusual departure.

The disappointing thing is that this chip on paper has the bandwidth - some pro users would likely be happy to get Zen 4 with the option for 0-2 PCIe 4.0x16 slots, and 2-6 PCIe 4.0x8 slots. That's the amount of bandwidth this CPU has.

Again there is no reduction in CPU lanes compared to AM4. There are 16 for the GPU, 4 for storage, 4 for secondary storage or USB 4 external PCIe, and 4 for the chipset to share put as desired. That's 28 total lanes just like AM4.

Chagall/Zen 3 did drop the TRX40 chipset but again the sWRX8 class was only a small uplift from prosumer anyways so I'm not sure the loss of sTR4 is all that interesting or best compared to AM5. The question is whether they decide to continue to release Threadripper Pros at an attractive price point not lamenting why AM5 didn't absorb sTR4.

PCI-E 5.0 has a ridiculous amount of bandwidth for consumer purposes. They just don't need as many lanes.

More lanes, more wires, higher complexity, higher cost.

Not surprising at all given that the same vendor thought it was fine stratagem to market a midrange dedicated GPU with only 4x PCIe 4.0 lanes. They are banking heavily on the trend of turning PCIe into a serial bus of sorts.

> on the trend of turning PCIe into a serial bus of sorts.

PCIe switches used to be far more common before certain things happened in the market and they became uber-expensive. I have a few NICs where, instead of using multi-port controllers, they just used PCIe switches... arguably I/O hubs have probably been the cheapest PCIe switches around for some time now...

Still haven't found anything compelling for PCIe4 but for PCIe3, I had no issues so far with 10Gtek, which are reasonably priced.

> They are banking heavily on the trend of turning PCIe into a serial bus of sorts.

It was always a serial bus? PCIe 1.0 was just too slow to handle everything without 16x systems. In fact, 32x slots/cards existed in the server market to make up for the missing bandwidth.

This only works if all devices are PCIe 5, though. There are still a lot of PCIe 3 or even PCIe 2 devices that could make do with very few PCIe 5 lanes but need a lot of lanes regardless.

Does an older device still occupy a whole lane right to the processor though? Or does the motherboard/chipset multiplex that onto a shared 5.0 lane into the CPU?

My read of it is the second, but I'd be happy to be shown wrong on this.

Only the CPU direct lanes are PCIe 5.0 and, being direct, none of that gets multiplexed. You either use all of a direct slot's assigned lanes at 5.0 speed or you miss out on that bandwidth.

Everything else not CPU direct (wired and wireless networking, SATA storage, non-primary USB ports, and 3 PCIe 4.0 addon cards) is connected via the chipset(s) which connect back via a single shared PCIe 4.0 x4 connection to the CPU. These are multiplexed but nothing here is using PCIe 5.0 bandwidth and even just 1 busy slot alone off this collection is able to consume the entire uplink bandwidth.

>this leaves a large gap for Intel to exploit with Alder Lake X.

Maybe the pricing you expect will be at a level that I am going to ignore anyways, but I think AMD may be reducing features and pci-e lanes because Intel has been doing just fine not giving away the kitchen sink in that area, at least from what I observe. Isn't intel kind of dragging their feet with any new HEDT lines?

If the amount of pins in the socket doesn't change significantly (as does between Ryzen and Threadripper) i doubt there will be any room for more PCI-E lanes, ever.