Re:Details on AMD's Quirky Chipset Solutions for AM5
by zamadatix on Sunday May 22, 2022 @11:51PM
(#31475175)
Only the CPU direct lanes are PCIe 5.0 and, being direct, none of that gets multiplexed. You either use all of a direct slot's assigned lanes at 5.0 speed or you miss out on that bandwidth.
Everything else not CPU direct (wired and wireless networking, SATA storage, non-primary USB ports, and 3 PCIe 4.0 addon cards) is connected via the chipset(s) which connect back via a single shared PCIe 4.0 x4 connection to the CPU. These are multiplexed but nothing here is using PCIe 5.0 bandwidth and even just 1 busy slot alone off this collection is able to consume the entire uplink bandwidth.
My read of it is the second, but I'd be happy to be shown wrong on this.