Re:Details on AMD's Quirky Chipset Solutions for AM5
by tedunangst on Sunday May 22, 2022 @10:37PM
(#31474868)
The three x4 links aren't sharing equally. One gets half bandwidth, two get a quarter each, when contended. If you're trying to read data off three drives, it's going to appear like one is twice as fast. But then you try to reproduce reading data off one drive at a time, and they all work at the same speed.
Re:Details on AMD's Quirky Chipset Solutions for AM5
by toast0 on Sunday May 22, 2022 @11:02PM
(#31474966)
Ok, but if you had 5 x4 drives before, one got full bandwidth from the cpu x4, and the other four would share (equally, I guess) on the chipset x4. Now, you'd get two on the uncontended cpu x4 lanes, and the three sharing (unequally, as you mention), seems slightly better that last time, but not an 'unusual departure' from the previous design; the CPU to chipset link is still very oversubscribed, but now, you can add a second oversubscribed chipset if you want, instead of having a choice between chipsets with different levels of oversubscription (or no chipset, only available in boards that don't expose most of the lanes)
AM4 cpus have an x16 for GPU, an x4 for NVMe storage, and an x4 for chipset, according to the article, AM5 cpus will have an x16 for GPU, an x4 for NVMe storage, and adds an x4 for for USB4 or more NVMe storage, and then an x4 for chipset, plus whatever the USB stuff means.
The rumored chipset takes that x4 and offers two x4s, four sata/3.0 x1 ports, and 6 usb3, six usb 2 ports.
There were a bunch of different chipsets for am4, most of which didn't have more connectivity than that. If you build the x670 link two of the new chipsets, and consider the added x4 from the cpu, you still have pretty similar connectivity as the x570, but you only have 12 lanes squeezing into the x4 for chipset instead of 16. There's certainly a discussion to be had about the CPU lanes being 5.0 and the chipset lanes (including uplink to the CPU, apparently) being 4.0; but while there's not much in the way of PCIe 5.0 devices, it's mostly hypothetical. If PCIe multiplexers weren't immensely expensive, the 24 CPU lanes at PCIe 5.0 would be equal to 48 lanes of PCIe 4.0 (plus 4 more for the chipset), and pretty close to the Zen2 Threadrippers's 56 + 8. Lack of cheap multiplexers means that's not really how the cookie crumbles though.