No - the example I gave above with multiple @(posedge clk) in the single always statement is synthesisable (by synopsys at least, I don't know about others) and contains an embedded loop - it's arguably a higher level way to make logic than the traditional always/case/state state machine. Maybe a simpler example will do:
always begin
@(posedge clk) v <= a+1;
@(posedge clk) v <= a-1;
end
always @(posedge clk) begin
v <= a+1;
@(posedge clk)
v <= a-1;
end
the shift register example you give would normally be synthesised to something with a synchronous clock and an async reset - during simulation the loop is waiting for either
Re:Verilog Is Weird
by magicalhippo on Friday March 25, 2022 @06:20AM
(#30800372)
> during simulation the loop is waiting for either
Ok, then we agree. Of course a simulator will have an implicit loop, that's not contentious.
However you did not mention this in your initial statement, and I've read and been told explicitly not to think of it like this because there's no loop in hardware.
If not, where in this shift register[1], when synthesized to an FPGA, is the loop waiting for posedge clk or posedge reset?
[1]: https://asic4u.wordpress.com/2016/03/28/verilog-1-delay-in-r...