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A comment on Verilog Is Weird. Parent comment

Re:Verilog Is Weird by Taniwha on Friday March 25, 2022 @02:33AM (#30799249)
the shift register example you give would normally be synthesised to something with a synchronous clock and an async reset - during simulation the loop is waiting for either
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Re:Verilog Is Weird by magicalhippo on Friday March 25, 2022 @06:20AM (#30800372)
> during simulation the loop is waiting for either

Ok, then we agree. Of course a simulator will have an implicit loop, that's not contentious.

However you did not mention this in your initial statement, and I've read and been told explicitly not to think of it like this because there's no loop in hardware.

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