No - the example I gave above with multiple @(posedge clk) in the single always statement is synthesisable (by synopsys at least, I don't know about others) and contains an embedded loop - it's arguably a higher level way to make logic than the traditional always/case/state state machine. Maybe a simpler example will do:

    always begin
        @(posedge clk) v <= a+1;
        @(posedge clk) v <= a-1;
    end

is identical to:

    always @(posedge clk) begin
        v <= a+1;
        @(posedge clk) 
        v <= a-1;
    end

both can be synthesised and make the same logic