Worth noting that TSMC is relentlessly incremental. While Intel wanted to make a bigger, slower jump from 14 to 10, TSMC did an N7, an N7+ (not to be confused with N7P), an N6, N5, and N5P, and later this year, N4 is on the roadmap.

So counting "generations" is a little abstract anyways. You should probably look at the PPA numbers and the kind of scaling boosters they've managed to ship, if you want to compare fairly.

> AFAIK Intel 10nm approximately equals TSMC 7nm.

I don't think so, TSMC 7nm is ahead in many ways. For example, Intel 10nm power efficiency is much worse.

https://blog.cloudflare.com/the-epyc-journey-continues-to-mi...

Intel 10nm is maybe more comparable with Samsung 8nm.

TSMC 7nm = Intel 10nm is a crazy old trope that dates back to before everyone realised that Intel couldn't deliver 10nm. I don't know why people keep repeating it.

Any node after they stopped measuring gate dimensions is a trope.

We need a better metric, a marketing term doesn’t work.

>TSMC 7nm is ahead in many ways. For example, Intel 10nm power efficiency is much worse.

Is this based on the lithography process, or because of the uarch?

The 7nm = 10nm was from https://en.wikichip.org/wiki/File:7nm_densities.svg, which looked at the density. Based comparison tables of lithography processes, it doesn't even look like power is something that they compare (eg. https://en.wikichip.org/wiki/7_nm_lithography_process)

In your second link there's Power @ iso-speed comparisons within TSMC's nodes and TSMC has 3 revisions of their N7 with 3 different power usages. Presumably, Intel can do similar things within their generations too.

The industry should really use a different metric like "transistor count / area" because in 5 years TSMC will need to either go negative NM or 0.99 to 0.001 nm to keep the marketing slogans going.

That would only make sense if all transistors were the same size.

They're not. Not even close. Especially, in combinational logic they're all over the place.

When verilog is being turned into gates there are many arguments the engineer can give the tool and they will give very different results. It's kinda like picking which optimizations get turned on during compile, like picking speed or binary size, although not exactly like that.

The industry tried using bit/area, because an important advantage of small transistors is more memory/area, but that has basically all the same complications as well so it doesn't really work like one wants.

So just counting transistors can be totally unfair when two designs are made for totally different applications.

In the end picking a node is a complicated, multi-dimensional, decision. Often, and more often than the public thinks, the smallest one is the wrong decision. Note: Google's TPU is at least a generation behind the bleeding edge, if not two, and not because Google can't afford it if they want to.

So, basically expect the marking names to continue for process node names for the foreseeable future.

For the more EE minded, see this deck: http://www.cse.psu.edu/~kxc104/class/cmpen411/14f/lec/C411L1...

If you don't want to go through the whole thing note slide 17 especially. Those are all the same boolean function but they have very different areas, speeds, and power. Which one the tool picks will be (mostly) controlled by the designer.

To the general reader, since maybe I have your attention, and maybe you like computer science and algorithms, let me direct your attention to:

DAG-Aware AIG Rewriting: A Fresh Look at Combinational Logic Synthesis http://people.eecs.berkeley.edu/~alanmi/publications/2006/da...

Which is the inspiration for this tool: https://github.com/berkeley-abc/abc

Which how this flow does synthesis: https://openroad.readthedocs.io/en/latest/

Ever heard of picometer?

Hasn't Intel put 10A on the roadmap? I guess 10A means 10 Atoms wide.

1 - 2 generations in the silicon world is 5 - 10 years

No? TSMC has a new "full node" (whatever that means now) every 2 years. And Intel 4 should be released the same year as TSMC N4.

Several is inclusive of two.

Only to a tiny minority of people: https://github.com/zonination/perceptions

The figure in your linked page looks like it is based on data from a survey in which participant were asked which number they thought of when they heard the word 'several'. Even if everyone taking the survey was aware that the word 'several' is inclusive of two, I'm not sure we would expect a different result. So, the results can't be used as evidence that anybody taking the survey did not think several is inclusive of two.