They're not. Not even close. Especially, in combinational logic they're all over the place.

When verilog is being turned into gates there are many arguments the engineer can give the tool and they will give very different results. It's kinda like picking which optimizations get turned on during compile, like picking speed or binary size, although not exactly like that.

The industry tried using bit/area, because an important advantage of small transistors is more memory/area, but that has basically all the same complications as well so it doesn't really work like one wants.

So just counting transistors can be totally unfair when two designs are made for totally different applications.

In the end picking a node is a complicated, multi-dimensional, decision. Often, and more often than the public thinks, the smallest one is the wrong decision. Note: Google's TPU is at least a generation behind the bleeding edge, if not two, and not because Google can't afford it if they want to.

So, basically expect the marking names to continue for process node names for the foreseeable future.

For the more EE minded, see this deck: http://www.cse.psu.edu/~kxc104/class/cmpen411/14f/lec/C411L1...

If you don't want to go through the whole thing note slide 17 especially. Those are all the same boolean function but they have very different areas, speeds, and power. Which one the tool picks will be (mostly) controlled by the designer.

DAG-Aware AIG Rewriting: A Fresh Look at Combinational Logic Synthesis http://people.eecs.berkeley.edu/~alanmi/publications/2006/da...

Which is the inspiration for this tool: https://github.com/berkeley-abc/abc

Which how this flow does synthesis: https://openroad.readthedocs.io/en/latest/