AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at 2 TB/SEC

Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by keanebean86 on Tuesday June 01, 2021 @12:39AM (#27350777)

So the next logical step would be to remove L3 cache from the compute chiplet all together? That would let AMD either save money since the chiplet is smaller or add more logic for the same die space.

This could also mean a GPU chiplet on package with compute. Each chiplet gets at least one cache layer. The next few years could be pretty crazy.

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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by Scene_Cast2 on Tuesday June 01, 2021 @12:44AM (#27350796)

Latency is still unclear, and probably worse than L3.

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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by Dylan16807 on Tuesday June 01, 2021 @02:18AM (#27351214)

If you're on a high end chip then you already have to talk to the other chiplet for half your L3. A stacked chip should be a lot faster than that.

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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by ece on Tuesday June 01, 2021 @06:21AM (#27352539)

The additional L3 is per chiplet, so you're still going to have to talk to other chiplets and their L3. Latency numbers would be good to see. This is definitely better than eDRAM L4 on the I/O die, and that's still something they could do, so props for that.

The power cost will really determine if we see this in Laptops or not though.

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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by Dylan16807 on Tuesday June 01, 2021 @03:11PM (#27359770)

> The additional L3 is per chiplet, so you're still going to have to talk to other chiplets and their L3.

You will sometimes, but traffic that still overflows to the other chiplet is probably almost all traffic that would have gone to RAM before.

And as a reference point, cross-chiplet L3 is about 50 nanoseconds slower than local L3. That will dwarf most things.

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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by coreblocks on Tuesday June 01, 2021 @01:15AM (#27350930)

Going over TSV will definitely incur at least one clock cycle.

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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by ksec on Tuesday June 01, 2021 @05:03PM (#27361261)

1. Latency ( One layer ) is the same, as updated in the article.

2. You will still ( for now ) need L3 Cache on the Chiplet where you have layers of SRAM on top.

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