Yes.

Intel is an industry leader. EFI, Thunderbolt, and the "ultrabook" product category are all their ideas. By adding a feature to their CPU products, they induce demand for anything that complements it.

By putting ECC support into their highest-end mobile CPUs only, they made them into high-end luxuries instead of industry standard. https://ark.intel.com/content/www/us/en/ark/search/featurefi...

As others have mentioned, ECC is nothing more than a bandaid for what is ultimately a defective product.

I don't think that's true at all. ECC wasn't designed specifically with this attack in mind, and it's still a pretty effective mitigation.

There's nothing defective about RAM, it's never going to be the case that errors won't happen, it's just that before we were worried about heat and radiation and now we have to worry about attackers too.

The Ultrabook brand was Intel's idea but I'm pretty sure it was created to make sure that the Wintel ecosystem could stay competitive with the MacBook Air.

That doesn’t explain Apple and the M1 though.

I am not familiar with DRAM spec sheets, but are manufacturers specifying that there will be zero errors?

Without a specification that says so, I don't think it's necessarily the fault of the manufacturer if they cannot build perfect RAM!

Suppose someone builds a car with one these computers in a safety-critical role, and then someone gets injured because of an error that "originated" with the RAM.

They specify timing and when it is followed, RAM should work without fault.

But if there are corner cases like this, they should be added to specs. Most likely it would require memory controller to remember last addresses and insert delays if rowhammer attempt is detected. And/or make CPU microoperation scheduler avoid it. No idea how expensive would that be, surely nontrivial.

There are already measures like that where the memory controller attempts to identify "victim rows" and refresh them, but attacks can fool the victim row detection and succeed anyway.

If my car's spec doesn't say "the wheels stay on" and then the wheels fall off, the car is still defective.

The true safety-critical stuff is far from ordinary and would never use commodity DRAM.

They could include ECC but it wouldn't work on most systems so why would they bother?

At least on AMD it works these days.

How many times more expensive would DRAM that is immune to rowhammer cost?

Not an expert, but I feel like the answer is not much. ECC RAM is not, to my knowledge, considerably more expensive to produce - the reason it costs more is because it only works with specific devices, so it's more of a market cost.

ECC RAM is pretty effective as-is against rowhammer, and imo you could very likely tweak ECC's approach to get even further.

The 'worst case' solution wouldn't be more than 2x, right? Since you'd just have to keep a clone of RAM, but obviously shuffled so that the same errors wouldn't occur in the same places. So 2x seems like the sort of absurd upper bound, but I feel like we could do a lot better.

My understanding is that rows in memory chips have thousands of bits in them. If you add 10-20 more to act as a refresh counter, then you can trigger extra refreshes if it gets high enough. Done right, that should give you immunity to rowhammer, while only costing a fraction of a percent in extra die space. And you won't be able to trick it like you can hash-table-based refresh counters.

Mid 2008 or so I think was when rowhammer-prone DRAM started appearing, so consider the density of that DRAM compared to today.