They specify timing and when it is followed, RAM should work without fault.

But if there are corner cases like this, they should be added to specs. Most likely it would require memory controller to remember last addresses and insert delays if rowhammer attempt is detected. And/or make CPU microoperation scheduler avoid it. No idea how expensive would that be, surely nontrivial.

There are already measures like that where the memory controller attempts to identify "victim rows" and refresh them, but attacks can fool the victim row detection and succeed anyway.

If my car's spec doesn't say "the wheels stay on" and then the wheels fall off, the car is still defective.

The true safety-critical stuff is far from ordinary and would never use commodity DRAM.