Feature size is super important in radiation exposed environments because resistance to bit flips from a stray proton (or other charged particles flying around in space) is inversely proportional to the size of your transistors. So small transistors mean they’re more likely to be activated by stray charged particles causing all kinds of interesting and exciting problems (which you don’t want to be debugging from one end of a 12 light minute comms channel).
Yup. And while the transistor sizes haven't really shrunk by the 35x that this suggests, they've still shrunk by a lot. And, of course, the area has shrunk by this amount squared.
> causing all kinds of interesting and exciting problems
Sometimes super exciting. Latchup can turn the whole package into a white-hot parasitic transistor connecting Vcore to ground at low impedance. Rad-hard variants can largely eliminate this possibility.
Keeping the working data synchronized would be the real trick. One could imagine all of these CPUs are hooked to a single bank of redundant and ECC stabilized memory, and all access goes through the watchdog processes which will only let through the ones that are in agreement.
The end result could be a system that is lighter and faster than the traditional RAD hardened system simply because it's built on a smaller process. The downside is the enormous complexity of the watchdog systems, they would be very expensive to get right. Also, synchronization is one of the hardest problems in computer science. It's basically cache invalidation on steroids.
This is a common set of techniques in critical systems. The smallsat built by students that I mentored didn't have voting, but it had processors with moderately sophisticated watchdogs performing mutual-power-monitoring and simple hardware failsafes. Aerospace control systems often run in lockstep and have voting, etc.
> Keeping the working data synchronized would be the real trick. One could imagine all of these CPUs are hooked to a single bank of redundant and ECC stabilized memory, and all access goes through the watchdog processes which will only let through the ones that are in agreement.
Typically you make the memory redundant too, and just ensure that input and outputs are common and all code is deterministic. e.g. There's Tandem / HP NonStop which use these techniques.
> The end result could be a system that is lighter and faster than the traditional RAD hardened system simply because it's built on a smaller process.
Handling upsets by voting makes a lot of sense. But radiation can cause permanent damage of small geometry circuits. And even with fast mechanisms to crowbar power in the event of a latchup, you're not really sure that you'll save the day.
It's a great way to handle things on the cheap for cutting edge payloads and research projects, though.
Tandem was software fault tolerant - the Stratus machines were fully hardware fault tolerant and ran code in parallel on seperate logical cpus to test for faults. Truly neat machines. Also, it was a PL/1 based machine - even the OS.
12(?) Motorola 68K chips were wired into multiple 'logical' cpu's, and programs executed in parallel on each. If a discrepancy arose, majority won and 'wrong' logical cpu's were taken out of service. It would also automatically call Stratus's remote service, report the failure and order a replacement board :-)
In plain English: an internal short-circuit.
Compare the PPC 740, which was ~300,000 transistors/mm^2 at 260nm. Apple M1 is ~130,000,000 transistors/mm^2 at 5nm. (260/5)^2 =~ 2700x, but the actual difference is ~430x.
So it's not as bad as line widths, but it still isn't quite keeping pace.
The node sizes used in marketing today haven't actually had any relation to feature size for at least 10 years. You can read some of the actual feature details for 7nm on wikipedia.
https://en.wikipedia.org/wiki/7_nm_process#7_nm_process_node...
If "feature size" is the width of a fin, a 7nm feature will typically be ~15nm across and spaced ~15nm apart (ie the center of one transistor is 30nm away from the center of the transistor next to it).
It's worth noting that the actual thickness of a transistor isn't strictly the most important factor. Which is why that wiki page shows fin pitch (the width of the transistor plus the space between transistors), because that's the metric that you get transistor density from.
This. Worked in physics department in the 90s that built satellites, and all the chips were late 70s or early 80s chips. Programming them was "fun".
Those old macs run Ubuntu just fine :)
It's actually a chronic problem with Voyagers 1/2. The teams that maintain them regularly experience weird, unplanned behavior because a cosmic ray bit-flipped some register or other, and then they have to manually figure out what erroneous command got executed and how to recover from it, and those are extremely simple systems compared to what's running on Perseverance.
So yeah, you need radiation hardened parts in space or you're just begging for a dead probe.
Case in point: https://www.jpl.nasa.gov/news/engineers-diagnosing-voyager-2...
"Engineers successfully reset a computer onboard Voyager 2 that caused an unexpected data pattern shift, and the spacecraft resumed sending properly formatted science data back to Earth on Sunday, May 23. Mission managers at NASA's Jet Propulsion Laboratory in Pasadena, Calif., had been operating the spacecraft in engineering mode since May 6. They took this action as they traced the source of the pattern shift to the flip of a single bit in the flight data system computer that packages data to transmit back to Earth. In the next week, engineers will be checking the science data with Voyager team scientists to make sure instruments onboard the spacecraft are processing data correctly. "
The single highest factor in all space design is cost per kg lifted. The only thing that is more costly - lifting it successfully and then having it break.
Heavier rover? You'll need more fuel for the skycrane's engines. And that fuel adds weight, so don't forget that you'll need more fuel to lift the extra fuel.
Now your rover and skycrane are bigger and heavier. Do you need a bigger parachute? Does everything still fit in the aeroshell? Is the fuel capacity for orienting and stabilizing the aeroshell still sufficient with the increased mass?
Detecting complete blackouts is fairly easy, after a while when a watchdog tickle is absent for too long, but bad output due to flipped memory? Consensus-style systems can be used, but they are also a complexity in itself, and the point here was to replace a hardened single point of failure with redundancy.
The CPUs used in space applications typically lag ~20 years behind the consumer market due to the need to be very sure that the kinks have been ironed out, and the need to produce variants that can withstand the environmental conditions outside earth's atmosphere.
EDIT: Also worth pointing out - the price of one of these specialized chips is in the six digits, due to the higher tolerances and low production volumes.