Looks like their Hard IP is proprietary but based on open high-level designs such as Rocket and BOOM. The peripherals situation is mixed, but they've stated in the past that they're quite OK with using open designs whenever feasible.

The high-level design is proprietary too.

As I said elsewhere, SiFive CPUs are just as closed as Arm ones, you just pay a royalty to SiFive instead of Arm.

> The high-level design is proprietary too.

They have source code files for their 'Freedom' core designs up on GitHub under an Apache 2.x license. These can be directly used to evaluate their designs as FPGA soft-cores.

The SoC, with the Rocket core used. This is very different from SiFive's own U series cores, which are proprietary.

SiFive has E-series (aka "Freedom Everywhere") and U-series (aka "Freedom Unleashed") cores, both of which seem to be based on Rocket. And they do provide high-level designs for both on their GitHub, under a free license.

High-level designs of the SoC, not of those cores themselves is public for some platforms.

Based on whatever for the core doesn't matter, as the cores themselves in any case diverge quite a lot from Rocket.

This is not correct. Anyone can design and build a RISC-V CPU without ever getting permission from anyone.

Anything that uses the ARM ISA on the other hand requires a (costly) licence from ARM.

SiFive has its own proprietary *implementation" buty that's not required, and there are many free open source implementations.

I wrote SiFive CPUs, not RISC-V there. (because this BeagleV board uses SiFive)

There's a _huge_ gap between academic implementations and ones that are actually worth shipping. I can see RISC-V winning quite handily for microcontrollers. But on anything bigger than that...

Western Digital's open sourced SweRV cores are approximately the same performance as the closed-source SiFive 7-series ones.

The main difference is the WD cores are 32 bit, no MMU, probably DTIM rather than cache (not sure).

The guts of the dual issue decode, register file, pipeline is there, which is the hard part. The other bits could be relatively easily added by the open source community, probably cribbing components from RocketChip.

People said that about open source compilers. Where are we now?

You need to give it a few years before you write it off. It's significant that most CS/EE students are now learning the RISC-V architecture.

They aren't for the customers of SiFive. What is your greater point with this comment? That SiFive isn't Open Source or that they are equivalent to Arm?

This video from SiFive clearly explains the RISC-V ecosystem and how SiFive is involved.

https://www.youtube.com/watch?v=CmGIJMYwWNw

Arm provides Verilog source code of their CPU cores for their customers. It's an industry standard practice.

You haven't said anything about SiFive.

Open source refers solely to the software side of things in these groups and types of projects. Thus, all of the drivers and software you need to use the SiFive is open source and thus you can say it is an open source design. However, it is not an "open hardware" design in that the IP used to design the chip is not released.

> However, it is not an "open hardware" design in that the IP used to design the chip is not released.

The marketing page for the BeagleV specifically says "Open Hardware Design", but I agree that they probably didn't mean Open Hardware beyond just the PCB layout or something similar.

It would be very surprising if they released the detailed schematics for the SiFive cores. Until there's some kind of common micro-fab standard where every major university can have a legit semiconductor fab for small scale operations, giving people the design doesn't really do much.

I really wish that someone would work on the problem of making affordable, small-scale semiconductor fabrication possible on a reasonably modern node (<= 32nm). It's a hard problem... but everyone in the world being dependent on a few large fabs is also a hard problem.

Correct. This is open at the ISA, PCB and software level, not the chip RTL.

Still, it is a step forward.

For something more open at the RTL level, I'd look at Precuror (https://www.crowdsupply.com/sutajio-kosagi/precursor) right now.

Speaking as someone at Beagle, we see this board as an important step to more openness in the ecosystem, especially helping software developers improve the state of open source for RISC-V. It is also just a really cool board. Beagle will do more to try to get more openness at the RTL-level moving forward, perhaps even with FPGA boards at an interim step. The shuttle services are starting to make releasing a new chip design in reasonably modern nodes more possible.

Some of them are open source: https://github.com/sifive/freedom

So this board has an open source CPU: https://www.sifive.com/boards/hifive1-rev-b

This does not: https://www.sifive.com/boards/hifive-unmatched

Although, I get the feeling they will open source design on a rolling basis. Pure speculation.

The processor maybe, but what about the e.g. USB3 controller, WIFI, etc, that can also freely snoop around your memory. Are there even open USB3 implementations?

> that can also freely snoop around your memory.

Can them? Even with IOMMU?

EDIT: I don't think so.

Is there an IOMMU specification standardized on RISC-V yet? I think it's just some early proposals.

Or proprietary designs that achieve similar functionality such as Hex Five and WorldGuard.

Am I right?