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Re:BeagleV – An affordable RISC-V computer designed to run L... by gjsman-1000 on Wednesday January 13, 2021 @09:11AM (#25762114)
Open source refers solely to the software side of things in these groups and types of projects. Thus, all of the drivers and software you need to use the SiFive is open source and thus you can say it is an open source design. However, it is not an "open hardware" design in that the IP used to design the chip is not released.
Re:BeagleV – An affordable RISC-V computer designed to run L... by coder543 on Wednesday January 13, 2021 @09:20AM (#25762217)
> However, it is not an "open hardware" design in that the IP used to design the chip is not released.

The marketing page for the BeagleV specifically says "Open Hardware Design", but I agree that they probably didn't mean Open Hardware beyond just the PCB layout or something similar.

It would be very surprising if they released the detailed schematics for the SiFive cores. Until there's some kind of common micro-fab standard where every major university can have a legit semiconductor fab for small scale operations, giving people the design doesn't really do much.

I really wish that someone would work on the problem of making affordable, small-scale semiconductor fabrication possible on a reasonably modern node (<= 32nm). It's a hard problem... but everyone in the world being dependent on a few large fabs is also a hard problem.

Re:BeagleV – An affordable RISC-V computer designed to run L... by jdkticom on Wednesday January 13, 2021 @10:16AM (#25762975)
Correct. This is open at the ISA, PCB and software level, not the chip RTL.

Still, it is a step forward.

For something more open at the RTL level, I'd look at Precuror (https://www.crowdsupply.com/sutajio-kosagi/precursor) right now.

Speaking as someone at Beagle, we see this board as an important step to more openness in the ecosystem, especially helping software developers improve the state of open source for RISC-V. It is also just a really cool board. Beagle will do more to try to get more openness at the RTL-level moving forward, perhaps even with FPGA boards at an interim step. The shuttle services are starting to make releasing a new chip design in reasonably modern nodes more possible.