As I said elsewhere, SiFive CPUs are just as closed as Arm ones, you just pay a royalty to SiFive instead of Arm.
They have source code files for their 'Freedom' core designs up on GitHub under an Apache 2.x license. These can be directly used to evaluate their designs as FPGA soft-cores.
Based on whatever for the core doesn't matter, as the cores themselves in any case diverge quite a lot from Rocket.
Anything that uses the ARM ISA on the other hand requires a (costly) licence from ARM.
SiFive has its own proprietary *implementation" buty that's not required, and there are many free open source implementations.
There's a _huge_ gap between academic implementations and ones that are actually worth shipping. I can see RISC-V winning quite handily for microcontrollers. But on anything bigger than that...
The main difference is the WD cores are 32 bit, no MMU, probably DTIM rather than cache (not sure).
The guts of the dual issue decode, register file, pipeline is there, which is the hard part. The other bits could be relatively easily added by the open source community, probably cribbing components from RocketChip.
You need to give it a few years before you write it off. It's significant that most CS/EE students are now learning the RISC-V architecture.
This video from SiFive clearly explains the RISC-V ecosystem and how SiFive is involved.