Dual ISA would be pretty cool. The more I learn about the differences between ARM and x86, the more it starts to seem like it really is not that much of a stretch. Just need the market for it.

At this point it seems more and more that x86 is still around purely due to legacy reasons and path-dependency. Intel's failure to execute on mobile really opened the door for ARM to have tons of resources over a decade thrown into it's development as a platform, and now the M1 is and extremely solid proof of concept that tentative forways into ARM on desktops/laptops/servers will absolutely warrant the shift in platforms. A few years for software ports and an extra 2 generations of chip improvements, and I think Intel's failure to execute on it's fab processes will just become a moot point. I have more confidence in AMD to pivot, and they have their GPU business as well. Intel may be relegated to aging obsolescence the same way HP and IBM did with their "big iron".

> Intel may be relegated to aging obsolescence the same way HP and IBM did with their "big iron".

Cough cough Itanium is an Intel-HP collaboration cough cough

Hah, true. That was absolutely the wrong chip at the wrong time, poorly implemented and lacking the software base of other platforms. I have no idea why they built the thing rather than put more resources behind Xeon, which was basically the end result anyway.

Multi-ISA chips have been announced from a couple of vendors (Loongson and Tachyum). The Loongson one does a MIPSish native ISA, MIPS, ARM, x86 and RISC-V, with the last three being slower.

https://www.zhihu.com/question/414069789 (needs Google Translate)

In the server market that could actually work, there are virtually no constraints on power or die size there.

There are plenty of constraints in the server markets. The primary ones are economic.

AMD, Nvidia, and Marvell after the Cavium acquisition could do it. Intel could too but wouldn’t unless the x86 market tanked badly.

> unless the x86 market tanked badly

That has always been a question of when, not if. And M1 shows that it is quickly approaching. In a market where physical limits have slowed down miniaturization, with just 5-10 years away from a standstill, a low efficiency instruction set focused on backwards binary compatibility is going to get washed out of most usecases very quickly. It's going the way of the IBM mainframe - still sold decades after its heyday, but marginalized to a niche (bunch of enterprise cloud instances for software that is too expensive to recompile/port).

M1's awesomeness has almost nothing to do with the instruction set. AMD64 and ARM64 are very similar in terms of complexity.

M1's awesomeness has to do with:

- assembling a killer team - 5nm process - high speed, low latency DRAM - big-little

The only substantive difference between the AMD64 and ARM64 instruction sets is that ARM64 has a more relaxed memory model.

Not true from what I’ve read. The problem with x86 is not complexity but variable instruction lengths. This makes it hard to determine instruction boundaries, complicating decoders and making more than 4-way decode hard. M1 has 8 decoders for comparison, and it would be easy to have 100 with ARM if there were a benefit to that many.

1. AMD64 is a lot easier to decode than the legacy i86 8/16/32 bit instruction set.

2. Decoding took a significant portion of the chip when they were a million transistors. The m1 has 16 billion resistors, decoding is a much less significant fraction of the chip.

Complexity isn't only about transistors, but also about delay.

And sure, there's pipelining but than your limited by latency.

> The limitation of the x86 decoder is that each clock cycle can only process up to 4 instructions, but if it is a familiar instruction, it can be placed in the operation cache, and 8 instructions can be processed per cycle.

http://www.apothetech.com/amd-zen-3-vs-zen-2-amd-zen-3-is-39...

Back in the Andy Grove era Intel exited its original business (memory) while it was profitable, foreseeing its rapid commoditization. The Intel of today sold off its excellent ARM business (acquired from DEC) and is incapable of doing anything but ride a sinking ship to doom.

At the time, StrongARM and PXA dominated PDAs and smartphones, while the higher-end parts were used in storage devices.

It's a little confusing still why they sold the whole thing while the market was growing.

Marvell seemingly abandoned portable devices and rolled IXP(?) into their own lines for a time.

Eh, Intel was so scared of itself it even stopped Atom getting properly powerful, and that was x86. No way they will get into the ARM team, the instant what they build starts being powerful they will get scared of it too and kill it.

A good part of why they take such a beating in x86 too, Intel has no backup plan because they're scared of their own backup up, while being oblivious to the fact that it was their backup plan that saved them during the post-P4 era.

At least AMD is not scared of throwing away their arch every few years and restart, they've pretty much been doing that like clockwork every five years for the past two decades.

It’s not the ISA that matters. But the execution of the project. Apple just showed it can make fast ARM. Is M1 faster than the latest zen?

No, it isn't. It's toe-to-toe on single core performance, sometimes faster, but slower in multicore.

Yeah but zen3 only pulls off matching M1 Firestorm by using 60% higher clock frequency and thus running a lot hotter.

At same clock frequency t he Zen3 would have been destroyed by the M1

Yes, but Apple also used their financial muscle to secure all of the 5nm capacity from TSMC. We're not comparing apples with apples here.

>Apple also used their financial muscle to secure all of the 5nm capacity from TSMC

It would be more accurate to describe Apple was the only customer willing to pay and has enough volume.

If you mean AMD couldn't match what Apple was willing to pay when you say "Apple was the only customer willing to pay", then absolutely. Otherwise, when push comes to shove in a bidding war with Apple, I don't think AMD really has a chance.

That's grossly mis-characterising the relationship between clock speed, performance and power consumption/heat dissipation in chip design.

And yet at the same power in multicore tasks Zen 2 outperforms the M1.

> Originally they were going to have a Zen variant that ran ARM.

Was AMD's K12 related to Zen in any way? AMD's predecessor to that, the Opteron A1100 series, was bog standard Cortex A57 cores. I figured K12 would be at best an evolution of a standard ARM design, but if it was more that would be very interesting. Would love to know more about this.

It wasn't a Zen variant; but the K12 was intended to be AMD's custom ARM uArch aimed at the server space. So there's a good chance it would have been focused on performance over power efficiency.

Power efficiency is an issue in the datacenter as well as you have to get that heat out, which also takes power.

I said over, as in relative to other ARM uArchs. Clearly, the power efficiency was the main draw of the proposal in the first place.