What do you want to do with it?

“Starting” is a bit ambiguous.

But I suggest that you first simple read the ISA specification. It’s surprisingly readable and if contains justifications for some design decisions.

After that, buy a small FPGA board and run a picorv32 CPU in it. Or one of the many other RISC-V soft cores.

Ah, I'm mostly hoping to learn how it works and what I can do with it. Trying to find a hardware-based pet project!

Buy yourself a TinyFPGA BX.

It’s a small (tiny!) FPGA board that’s still large enough to run a RISC-V CPU. It’s a full open source flow. And there are plenty of examples.

Get that first LED blinking!

Or an UPduino which is still cheaper. I've had good experiences with one, though I'm only at the "PWM-animated LED" stage right now.

Oh, and https://www.nand2tetris.org is great. You implement a simple CPU, and though the language isn't a real-world one you learn enough to probably be able to implement a similar CPU on an FPGA using VHDL or Verilog.

Since RISC-V uses Chisel instead of Verilog, you will probably need this first: https://github.com/freechipsproject/chisel-bootcamp

For actually learning RISC-V, you can check out these books: https://riscv.org/risc-v-books/

The Patterson and Hennessy book is a great starting point and the RISC-V reader is great reference.

The error is understandable, the main prototype RISC-V core is written in Chisel and the "Rocket Core Generator" is written in Chisel. The RISC-V team at Berkeley has a lot of overlap with the Chisel team. So it is easy to think RISC-V is all Chisel. I believe Chisel, Chisel, RISC-V, Chisel, if that makes any sense.

https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-ch...

https://github.com/freechipsproject/rocket-chip (parametric SoC generator, Chisel)

https://github.com/ucb-bar/riscv-sodor (Chisel)

https://chisel.eecs.berkeley.edu/

Yup I'm an idiot but I can't seem to delete or edit my original submission :c

Thank you for the information.

Ur good. Chisel.

> Since RISC-V uses Chisel instead of Verilog

What do you mean? The core here is entirely Verilog/SystemVerilog

I presume the parent generalized their experience with the BOOM and Rocket implementations of RISC-V, which do use Chisel, to the entire architecture.

Sorry I am an idiot how do I edit/delete my comment so I can erase this misinformation?

Unfortunately, if you don't see an edit button on the comment then you can't edit it anymore. But props for admitting you're wrong and trying to correct it :-)

> Since RISC-V uses Chisel instead of Verilog

How can an ISA ‘use Chisel’? It’s a spec not an implementation.