Verilog sources for Western Digital's open source RISC-V core

Re:Verilog sources for Western Digital's open source RISC-V ... by dooglius on Saturday January 26, 2019 @09:58PM (#19010115)

> Since RISC-V uses Chisel instead of Verilog

What do you mean? The core here is entirely Verilog/SystemVerilog

[ Parent | on HN ]

Re:Verilog sources for Western Digital's open source RISC-V ... by mepian on Saturday January 26, 2019 @10:06PM (#19010135)

I presume the parent generalized their experience with the BOOM and Rocket implementations of RISC-V, which do use Chisel, to the entire architecture.

[ Parent | on HN ]

Re:Verilog sources for Western Digital's open source RISC-V ... by eBombzor on Saturday January 26, 2019 @11:59PM (#19010409)

Sorry I am an idiot how do I edit/delete my comment so I can erase this misinformation?

[ Parent | on HN ]

Re:Verilog sources for Western Digital's open source RISC-V ... by yjftsjthsd-h on Sunday January 27, 2019 @12:04PM (#19012555)

Unfortunately, if you don't see an edit button on the comment then you can't edit it anymore. But props for admitting you're wrong and trying to correct it :-)

[ Parent | on HN ]