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A comment on Verilog sources for Western Digital's open source RISC-V core. Parent comment

Re:Verilog sources for Western Digital's open source RISC-V ... by chrisseaton on Saturday January 26, 2019 @10:21PM (#19010183)
> Since RISC-V uses Chisel instead of Verilog

How can an ISA ‘use Chisel’? It’s a spec not an implementation.

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