Verilog sources for Western Digital's open source RISC-V core

Re:Verilog sources for Western Digital's open source RISC-V ... by sitkack on Sunday January 27, 2019 @12:40AM (#19010490)

The error is understandable, the main prototype RISC-V core is written in Chisel and the "Rocket Core Generator" is written in Chisel. The RISC-V team at Berkeley has a lot of overlap with the Chisel team. So it is easy to think RISC-V is all Chisel. I believe Chisel, Chisel, RISC-V, Chisel, if that makes any sense.

https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-ch...

https://github.com/freechipsproject/rocket-chip (parametric SoC generator, Chisel)

https://github.com/ucb-bar/riscv-sodor (Chisel)

https://chisel.eecs.berkeley.edu/

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Re:Verilog sources for Western Digital's open source RISC-V ... by eBombzor on Sunday January 27, 2019 @12:56AM (#19010531)

Yup I'm an idiot but I can't seem to delete or edit my original submission :c

Thank you for the information.

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Re:Verilog sources for Western Digital's open source RISC-V ... by sitkack on Sunday January 27, 2019 @02:54AM (#19010796)

Ur good. Chisel.

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