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Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by deepnotderp on Wednesday August 16, 2017 @12:05AM (#15024870)
Okay, so the node names are effectively useless at this point. They used to refer to gate length, but no longer, even for Intel. Oh, and Intel's 10nm will actually have lower performance than their 14nm.

Besides, it matters not, the bottlenecks today are in memory and interconnects.

Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by Dylan16807 on Wednesday August 16, 2017 @12:54AM (#15025024)
> Oh, and Intel's 10nm will actually have lower performance than their 14nm.

Less than 14++, sure, but 10+ and 10++ will fix that.

Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by deepnotderp on Wednesday August 16, 2017 @01:17AM (#15025108)
Yes, but I was just pointing out that scaling is now neither a panacea nor free.
Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by likelynew on Wednesday August 16, 2017 @07:22AM (#15026598)
Performance compared to what? Same power, Same price, or just the performance of the fastest processor of the series?
Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by ktRolster on Wednesday August 16, 2017 @01:01AM (#15025050)
At some point, maybe we'll start seeing RAM put onto the CPU itself.

I mean, more than it already is (with cache).

Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by zerohp on Wednesday August 16, 2017 @01:17AM (#15025107)
You will see stacked memory and silicon interposers, but you won't see main memory on the CPU die. DRAM is based on an array of what is called "trench capacitors." The fabrication process is sufficiently different that they don't even make these in the same facility, much less on the same die process. An array of trench capacitors will always be smaller than transistor based memory (SRAM.)
Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by deepnotderp on Wednesday August 16, 2017 @01:19AM (#15025119)
There are alternatives on the horizon, e.g. STT-RAM, MRAM, memristors, PCMs, ReRAM (same as memristors according to some...), spintronic devices, etc.

There are also other attempts such as FBRAM to replicate DRAM structures without the need for insane A/R trench capacitors.

I believe that such solutions are necessary to continue scaling.

Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by baybal2 on Wednesday August 16, 2017 @09:03AM (#15027100)
It is not a big problem to make DRAM on pretty much every SOI process, just power consumption and refresh rates will have to be quite big.

The problem with MRAM is unreliable reads, they are excellent for low clock speed devices, but as you go into gigahertz range, signal quality of an mram cell begins to degrade, and you have to put a darlington on top of it, or a bicmos transistor, thus negating its cell size advantage

Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by deepnotderp on Wednesday August 16, 2017 @11:31AM (#15028282)
For DRAM are you talking about standard deep tech capacitor dram or FBRAM?

Agree with MRAM, but it is also a very immature technology, so there's hope at least. unless you're talking about crossbar crosstalk which can be solved with a diode.

Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by baybal2 on Wednesday August 16, 2017 @08:51PM (#15032742)
About floating body ram and others that rely on capacitance of the substrate itself rather than a dedicated capacitor
Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by deepnotderp on Wednesday August 16, 2017 @11:03PM (#15033483)
Ah, I see. But it's not significantly higher than other DRAMs, right? At least last I checked the difference wasn't that big.
Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by baybal2 on Thursday August 17, 2017 @07:49AM (#15035834)
I believe that data published by people peddling embedded dram ip is their "best case scenario" with still significant alteration to manufacturing process