Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake

Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by baybal2 on Wednesday August 16, 2017 @09:03AM (#15027100)

It is not a big problem to make DRAM on pretty much every SOI process, just power consumption and refresh rates will have to be quite big.

The problem with MRAM is unreliable reads, they are excellent for low clock speed devices, but as you go into gigahertz range, signal quality of an mram cell begins to degrade, and you have to put a darlington on top of it, or a bicmos transistor, thus negating its cell size advantage

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Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by deepnotderp on Wednesday August 16, 2017 @11:31AM (#15028282)

For DRAM are you talking about standard deep tech capacitor dram or FBRAM?

Agree with MRAM, but it is also a very immature technology, so there's hope at least. unless you're talking about crossbar crosstalk which can be solved with a diode.

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Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by baybal2 on Wednesday August 16, 2017 @08:51PM (#15032742)

About floating body ram and others that rely on capacitance of the substrate itself rather than a dedicated capacitor

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Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by deepnotderp on Wednesday August 16, 2017 @11:03PM (#15033483)

Ah, I see. But it's not significantly higher than other DRAMs, right? At least last I checked the difference wasn't that big.

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Re:Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake by baybal2 on Thursday August 17, 2017 @07:49AM (#15035834)

I believe that data published by people peddling embedded dram ip is their "best case scenario" with still significant alteration to manufacturing process

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