You will see stacked memory and silicon interposers, but you won't see main memory on the CPU die. DRAM is based on an array of what is called "trench capacitors." The fabrication process is sufficiently different that they don't even make these in the same facility, much less on the same die process. An array of trench capacitors will always be smaller than transistor based memory (SRAM.)

There are alternatives on the horizon, e.g. STT-RAM, MRAM, memristors, PCMs, ReRAM (same as memristors according to some...), spintronic devices, etc.

There are also other attempts such as FBRAM to replicate DRAM structures without the need for insane A/R trench capacitors.

I believe that such solutions are necessary to continue scaling.

It is not a big problem to make DRAM on pretty much every SOI process, just power consumption and refresh rates will have to be quite big.

The problem with MRAM is unreliable reads, they are excellent for low clock speed devices, but as you go into gigahertz range, signal quality of an mram cell begins to degrade, and you have to put a darlington on top of it, or a bicmos transistor, thus negating its cell size advantage

For DRAM are you talking about standard deep tech capacitor dram or FBRAM?

Agree with MRAM, but it is also a very immature technology, so there's hope at least. unless you're talking about crossbar crosstalk which can be solved with a diode.

About floating body ram and others that rely on capacitance of the substrate itself rather than a dedicated capacitor

Ah, I see. But it's not significantly higher than other DRAMs, right? At least last I checked the difference wasn't that big.

I believe that data published by people peddling embedded dram ip is their "best case scenario" with still significant alteration to manufacturing process