Honestly, I'd wager it's because Verilog and VHDL suck in a lot of ways basically. They work, but almost anything has better abstraction and reuse capabilities, even embedded DSLs or bespoke compilers or whatever, and offer better feedback loops during development. REPLs help a lot when building big circuits out of smaller ones. Being able to use a package manager to grab and manage SoC/IP components is convenient, etc.

Most of these DSLs tend to work at the level of RTL as opposed to something like "high level synthesis" where register usage is inferred, too (OpenCL, C, etc). So depending on how it's designed the results can be pretty close to hand-written code IME, without much overhead. They're more like "Super RTL" as opposed to real "high level" languages...

I suspect you're right, but it makes me sad. I really like verilog as a language and after working with it for a few years wish it was possible to program desktops in a similar way.

I was exactly in the same mood some years ago, until i triey one of those HDL alternative.

I'm not sure about the trend in general, but it looks like SpinalHDL is a fork of Chisel, the 'other' Scala-based HDL.

Yes kind of, SpinalHDL is a from scratch fork

Everybody wants a new HDL but there's no standard yet. Embedding it in your favourite language is the obvious solution, and hence there will be at least one per language.

Yes a standard would be great, with all the feature provide by those embedded HDL, but i'm realy not sure the industry could make it. #systemverilog