An FPGA-friendly 32-bit RISC-V CPU implementation

Re:An FPGA-friendly 32-bit RISC-V CPU implementation by rvense on Wednesday July 19, 2017 @03:23PM (#14807096)

Everybody wants a new HDL but there's no standard yet. Embedding it in your favourite language is the obvious solution, and hence there will be at least one per language.

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Re:An FPGA-friendly 32-bit RISC-V CPU implementation by Dolu on Wednesday July 19, 2017 @05:37PM (#14808201)

Yes a standard would be great, with all the feature provide by those embedded HDL, but i'm realy not sure the industry could make it. #systemverilog

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