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A comment on An FPGA-friendly 32-bit RISC-V CPU implementation. Parent comment

Re:An FPGA-friendly 32-bit RISC-V CPU implementation by Dolu on Wednesday July 19, 2017 @05:37PM (#14808201)
Yes a standard would be great, with all the feature provide by those embedded HDL, but i'm realy not sure the industry could make it. #systemverilog
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