An FPGA-friendly 32-bit RISC-V CPU implementation

Re:An FPGA-friendly 32-bit RISC-V CPU implementation by debatem1 on Thursday July 20, 2017 @01:32AM (#14810214)

I suspect you're right, but it makes me sad. I really like verilog as a language and after working with it for a few years wish it was possible to program desktops in a similar way.

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Re:An FPGA-friendly 32-bit RISC-V CPU implementation by Dolu on Thursday July 20, 2017 @05:24AM (#14811050)

I was exactly in the same mood some years ago, until i triey one of those HDL alternative.

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