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A comment on An FPGA-friendly 32-bit RISC-V CPU implementation. Parent comment

Re:An FPGA-friendly 32-bit RISC-V CPU implementation by baobrien on Wednesday July 19, 2017 @03:09PM (#14806977)
I'm not sure about the trend in general, but it looks like SpinalHDL is a fork of Chisel, the 'other' Scala-based HDL.
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Re:An FPGA-friendly 32-bit RISC-V CPU implementation by Dolu on Wednesday July 19, 2017 @05:19PM (#14808041)
Yes kind of, SpinalHDL is a from scratch fork
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