> Neural nets are honestly best suited to a ZISC type architecture... In any case, specialized deep learning chips should be on their way.

Google's TPU architecture is CISC type instead of ZISC type: https://www.nextplatform.com/2017/04/05/first-depth-look-goo...

I don't actually think that the Google TPU is the paragon of deep learning processor architecture, there are a lot of things that I don't think are done very well.

In any case, that being said, the TPU is less of a CISC and much more like a lightweight RISC control mechanism.

I don't really agree. What is labelled a "CISC instruction set" here would more usually just be called a control interface. But maybe I'm missing some sort of context here. (Contrasting it with "ZISC" for marketing purposes?)

> Contrasting it with "ZISC" for marketing purposes?

I don't understand what you want to say: ZISC is a rather different concept: https://en.wikipedia.org/wiki/Zero_instruction_set_computer

It's almost always better to have a dedicated chip implement some algorithm, if it makes economic sense to do so. From hard drive controllers to Google's TPU.

Deep learning processor != an ASIC

If you burned an ASIC for a single type of network architecture, then that would be something else.

The TPU is an ASIC.

The result is called a Tensor Processing Unit (TPU), a custom ASIC we built specifically for machine learning.

https://cloudplatform.googleblog.com/2016/05/Google-supercha...

Perhaps it's a confusion of terminology, because most people I know would call it as asip. It has the flexibility to implement any linear operation after all.

Is there any systems out there that would let me program on a ZISC, today?