How Many X86-64 Instructions Are There Anyway?

Re:How Many X86-64 Instructions Are There Anyway? by wolfgke on Sunday April 30, 2017 @06:23PM (#14234200)

> Neural nets are honestly best suited to a ZISC type architecture... In any case, specialized deep learning chips should be on their way.

Google's TPU architecture is CISC type instead of ZISC type: https://www.nextplatform.com/2017/04/05/first-depth-look-goo...

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Re:How Many X86-64 Instructions Are There Anyway? by deepnotderp on Sunday April 30, 2017 @07:06PM (#14234377)

I don't actually think that the Google TPU is the paragon of deep learning processor architecture, there are a lot of things that I don't think are done very well.

In any case, that being said, the TPU is less of a CISC and much more like a lightweight RISC control mechanism.

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Re:How Many X86-64 Instructions Are There Anyway? by dom0 on Sunday April 30, 2017 @06:29PM (#14234222)

I don't really agree. What is labelled a "CISC instruction set" here would more usually just be called a control interface. But maybe I'm missing some sort of context here. (Contrasting it with "ZISC" for marketing purposes?)

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Re:How Many X86-64 Instructions Are There Anyway? by wolfgke on Sunday April 30, 2017 @06:38PM (#14234262)

> Contrasting it with "ZISC" for marketing purposes?

I don't understand what you want to say: ZISC is a rather different concept: https://en.wikipedia.org/wiki/Zero_instruction_set_computer

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