Not to toot my own horn here, but we're one of the hopeful deep learning chip startups, I'd be happy to answer any more questions or perhaps elaborate on why I think ZISC is better for neural nets.
Google's TPU architecture is CISC type instead of ZISC type: https://www.nextplatform.com/2017/04/05/first-depth-look-goo...
In any case, that being said, the TPU is less of a CISC and much more like a lightweight RISC control mechanism.
I don't understand what you want to say: ZISC is a rather different concept: https://en.wikipedia.org/wiki/Zero_instruction_set_computer
If you burned an ASIC for a single type of network architecture, then that would be something else.
The result is called a Tensor Processing Unit (TPU), a custom ASIC we built specifically for machine learning.
https://cloudplatform.googleblog.com/2016/05/Google-supercha...
I tend to think of "CISC" as complex instruction encodings, smaller register files, complex sets of addressing modes, lack of orthogonality in instructions, etc. None of these aspects are gaining in popularity for new designs. The only one I can think of that gained any popularity is Thumb-like compressed instruction sets, which aren't so much "CISC" as "don't spend opcode space for no reason".