inforichland

Exactly, that's how I would (hopefully will soon) implement it as well; it takes a few extra cycles but avoids extra overhead.

I am still leery of the "unconventional" HDLs. I don't really see many of them as much of an improvement over say, VHDL-2008; you get records and functions and instantiation is not as verbose. Yes, the language is a little wordy but it's well proven and I already know it; and many other people know as well, so they can read it and understand it better w/o learning a new language.

Thank you :) Also thanks for the information; I had been wondering if someone had made some more thorough automated tests, I will definitely check those out!

Honestly, I'm still on the new-ish end of FPGA design (a year or so), so I'm probably not qualified to answer the first one, but I'd have to guess probably not much faster? A fully pipelined CPU could theoretically achieve the maximum clock rate that a given FPGA family could support (i.e. not more than 1 level of logic b/w flops). Actually, yes you could write your own BIOS in some HDL; there are several FPGA dev board that are "USB sticks." See [1] and [2].

[1] http://www.latticesemi.com/en/Products/DevelopmentBoardsAndK... [2] http://www.altera.com/b/nios-bemicro-evaluation-kit.html

Yes, I have seen it, and I have used it a few times. For some types of modules, I really do like how it separates out the state from the logic itself; as a person who started writing firmware first, and then started logic design, the two-process method can make it feel less like software sometimes.

Everything I've read these days says to use numeric_std (I've read the reasons why, and it makes sense), so I just never even bothered using the std_logic_*signed libraries. I'll check out your MIPS project; I'm intending my next project to be a fully pipelined RISC machine :-)

Most likely it would be faster, as the Forth primitive words are implemented in hardware. The single-cycle words are: +, -, 2*, 2/, dup, not, @, !, >r, drop, r>, rot, -rot, swap, nip, tuck, over, =. Un/conditional jumps and calling a word take 2 cycles. Naturally, though, this only makes sense if you already have an FPGA in your design.

I guess the unstated goal of this was to create a small, simple and fast soft-core processor that could be used to augment FPGA designs (<15% of a small devices resources @ 100MHz).

Honestly, I wrote this just to scratch an itch. I've always loved the elegance of Forth, and having stumbled upon (http://users.ece.cmu.edu/~koopman/stack_computers/index.html) that, I decided to create my own, with the goal of having single-cycle execution of all non-control-flow operations. Having said that, one could easily take it, and probably fairly quickly implement the Forth interpreter and use it in a classroom if they desired. I guess the explicit goal was an embedded node, but it's fairly flexible.