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A comment on Show HN: A pipelined RISC-V processor written in VHDL. Parent comment

Re:Show HN: A pipelined RISC-V processor written in VHDL by inforichland on Tuesday July 28, 2015 @09:05PM (#9965679)
Exactly, that's how I would (hopefully will soon) implement it as well; it takes a few extra cycles but avoids extra overhead.
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