Re:Show HN: A pipelined RISC-V processor written in VHDL
by inforichland on Tuesday July 28, 2015 @09:04PM
(#9965672)
I am still leery of the "unconventional" HDLs. I don't really see many of them as much of an improvement over say, VHDL-2008; you get records and functions and instantiation is not as verbose. Yes, the language is a little wordy but it's well proven and I already know it; and many other people know as well, so they can read it and understand it better w/o learning a new language.
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Re:Show HN: A pipelined RISC-V processor written in VHDL
by sklogic on Wednesday July 29, 2015 @04:42AM
(#9967142)
Higher level generator HDLs shine when you want something heavily parametric. VHDL and Verilog code generation features are way too weak, so having a higher level meta-language helps a lot.