Then we complain to them when it misbehaves anyway. A quick google will you find some guides.

https://www.doulos.com/knowhow/vhdl_designers_guide/rtl_codi...

On top of that we had company specific style guides. Having jumped from company to company, each one is different here and there.

To be honest, I think we tended to avoid looking at other people's code when we could! Its like having to wipe someone else's butt. It all looks terrible. Everyone can pick on someone else's stuff.

Having said all that, the basic principles of engineering apply:

- Nice separation between the design and the test bench.

- modularity within the design itself.

- A convention of signal naming that will assist the verification process. Eventually they get thrown a waveform when something has gone wrong. They need to look at signal names that aren't some random alphabet jumble.

- Parameterize variables so they can be reconfigured easily.

etc.

There's also value to a consistently styled codebase.

Maybe it's time for me to add another one: good Verilog RTL coding style, or basic RTL rules for Verilog... Based on the kinds of mistakes I see online, it would be easy to cover initial blocks, multiple assignments, etc.

EDIT: just started https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_RTL... . For now, just contains placeholders for the items I want to cover, but feel free to add to the list, that's the whole point of a wiki.