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A comment on Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching. Parent comment
Maybe it's time for me to add another one: good Verilog RTL coding style, or basic RTL rules for Verilog... Based on the kinds of mistakes I see online, it would be easy to cover initial blocks, multiple assignments, etc.
EDIT: just started https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_RTL... . For now, just contains placeholders for the items I want to cover, but feel free to add to the list, that's the whole point of a wiki.
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Maybe it's time for me to add another one: good Verilog RTL coding style, or basic RTL rules for Verilog... Based on the kinds of mistakes I see online, it would be easy to cover initial blocks, multiple assignments, etc.
EDIT: just started https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_RTL... . For now, just contains placeholders for the items I want to cover, but feel free to add to the list, that's the whole point of a wiki.