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Re:Designing a CPU in VHDL, Part 6: Program Counter, Instruc... by gluggymug on Thursday July 23, 2015 @08:54PM (#9939462)
Tools vendors each have coding guidelines that their stuff likes. At the RTL level, industry guys like myself just follow them like puppies due to fear of something in the tool chain breaking.

Then we complain to them when it misbehaves anyway. A quick google will you find some guides.

https://www.doulos.com/knowhow/vhdl_designers_guide/rtl_codi...

On top of that we had company specific style guides. Having jumped from company to company, each one is different here and there.

To be honest, I think we tended to avoid looking at other people's code when we could! Its like having to wipe someone else's butt. It all looks terrible. Everyone can pick on someone else's stuff.

Having said all that, the basic principles of engineering apply:

- Nice separation between the design and the test bench.

- modularity within the design itself.

- A convention of signal naming that will assist the verification process. Eventually they get thrown a waveform when something has gone wrong. They need to look at signal names that aren't some random alphabet jumble.

- Parameterize variables so they can be reconfigured easily.

etc.

Re:Designing a CPU in VHDL, Part 6: Program Counter, Instruc... by sliverstorm on Friday July 24, 2015 @01:44AM (#9940272)
industry guys like myself just follow them like puppies due to fear of something in the tool chain breaking

There's also value to a consistently styled codebase.