The Epiphany cores have no cache.

EDIT: And if you want to read/write the same memory areas from multiple cores, it's your own responsibility to either get the timing right, or use other means (e.g. you can trigger interrupts in another core) to signal when it is safe for another core to access data.

I'd imagine it works like a Transputer, and the only accessible memory is local to the chip, with communications including data coming down the serial links.

The chips have a flat address space that covers any Epiphany chips that have been interconnected via the serial links, and the main memory of the CPU.

You can address core-local memory, memory in another core, or main memory the same way - the difference is speed.

There's no cache, and you're responsible for avoiding race conditions in memory access yourself.