Re:The 64-core Parallella is alive
by watmough on Monday April 28, 2014 @09:06PM
(#7664233)
I'd imagine it works like a Transputer, and the only accessible memory is local to the chip, with communications including data coming down the serial links.
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The chips have a flat address space that covers any Epiphany chips that have been interconnected via the serial links, and the main memory of the CPU.
You can address core-local memory, memory in another core, or main memory the same way - the difference is speed.
There's no cache, and you're responsible for avoiding race conditions in memory access yourself.