I said that exactly. Half the cpu will be cache and it only helps once data is in the cache, which it won't be if you are running through big arrays. Big arrays would be necessary to supply a bunch of tiny cores, unless of course you had prefetching and other mechanics.
When its all in cache it runs at basically full speed.
L3 cache will not run at full speed. The latency is much better but you still have 40 cycles. That means that every lda instruction will wait for 40 cycles when in old computers it would take one cycle. That's just for anything already in cache, not the 500 cycles you would stall for something outside of cache. Don't forget that there are no cache lines and no out of order execution so you pull down a single byte after 500 cycles and if you read the next byte you wait 500 more cycles.
Thats all true but what im suggesting is if you had MORE a lot MORE humble cpus even if they run at a much less than GHZ
Your idea is clear, it's not a misunderstanding, it's just something that has been considered a long time ago and dismissed.
Think a lot of slow donkeys would still get move more than a ferrari, for less money and less fuel.
People don't want slow donkeys, they want to move themselves with a ferrari or jet, or huge amounts of stuff on a giant ship. Donkeys are obsolete. They don't cross water, they don't move fast, they don't go straight.
Thats all true but the cost of that performance is a lot of heat and silicon.
So what?
What if that power was given to a million 6510s ?
You would have the same number of transistors and you would be able to do 0 floating point calculations because those CPUs had no floating point units. You can't even multiply integers. You can add and subtract integers. Now you have to sit and wait on every memory load, you have lower Ghz and every math operation is going to use lots and lots of cycles because you can't even multiply integers. Good luck with that.
The 6510 did not have any cache. Im suggesting the cost/benefit of cpus that do not have any cache, no branch prediction, no out of order, just the minimum to execute its ISA.
Again cutting things down to as simple as possible and hope for the best.
> Your idea is clear, it's not a misunderstanding, it's just something that has been considered a long time ago and dismissed
It was dismissed because x86 has a very large impossibly expensive range of software that would be lost on any new different arch.
> You would have the same number of transistors and you would be able to do 0 floating point calculations because those CPUs had no floating point units.
The 6510 could do floating point in software. Im not saying that the solution must be a million 6510, one could add a simple FPU and advance some of the features. Im just suggesting an arch without all the extras that require lots of transistors like Out of order execution, caches and all that.
Right, again this is clear. Although you did talk about cache earlier, it's not a mystery what you are trying to say. It's simple, easy and doesn't work.
Again cutting things down to as simple as possible and hope for the best.
These old CPUs are extremely efficient with transistor budgets but they do almost nothing.
It was dismissed because x86 has a very large impossibly expensive range of software that would be lost on any new different arch.
This is completely wrong. If this architecture worked, there would be a 100,000 original x86 cores on a chip. You can look at the evolution of x86, super scalar computers like cray machines, the successors to the 6502, chips from sun, dec, SGI etc. and see what they added and why.
There are new CPUs running riscv that you can buy right now and they don't do anything like this even though it is running on a completely new instruction set.
The 6510 could do floating point in software.
32 or 64 bit floating point numbers using just 8 bit integer add and subtract with bit shifts. Kind of seems like the thing that would be much better done in hardware. Maybe do 8 or 16 floating point operations in a single cycle.
one could add a simple FPU
The first FPU was 45,000 transistors. Now each chip isn't 3,500 transistors any more. Don't forget you are still moving single bytes around with every instruction, many instructions take more than one cycle to complete, you have almost no registers and the ones you have are all 8 bit and because you have no cache, every memory load takes hundreds of cycles while the cpu sits and does nothing.
Im just suggesting an arch without all the extras that require lots of transistors like Out of order execution, caches and all that.
Again, it's obvious that you are suggesting that and with a little research it's obvious why it doesn't work out.
Waiting for those periods only occurs when a modern cpu is fetching memory outside its caches. When its all in cache it runs at basically full speed.
> To counter act that you need prefetching so you can get from memory ahead of time etc. This goes on and on until you either build a modern CPU or a modern GPU.
Thats all true but what im suggesting is if you had MORE a lot MORE humble cpus even if they run at a much less than GHZ, doing a little work the sum of the humble cpus would actually become more than the modern fast cpu.
Think a lot of slow donkeys would still get move more than a ferrari, for less money and less fuel.
> Then finally there are modern GPUs which already can do one million floating point operations in the time it takes to get a single byte from memory (the single byte is really two cache lines which is the minimum and this also includes the memory not being in the TLB).
Thats all true but the cost of that performance is a lot of heat and silicon.
What if that power was given to a million 6510s ?