They spent way too long procrastinating, with zero silicon after decades of work.

For comparison, RISC-V started years later and had a tapeout within a year and working silicon available as a commercial product in seven years.

2003: Mill computing started

2010: RISC-V project started

2011: RISC-V first tapeout

2017: RISC-V production chips available in the market

2019: Mill computing dead?

Yeah, but RISC-V came out of RISC-1,2,3,4; it didn't magically appear our of nowhere. "RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the university since 1981".

Also, RISC-V is not particularly innovative or groundbreaking. It's a standard Von Neumann CPU optimised for simplicity and modularity.

The Mill was (is?) a much bigger swing, with much bigger problems to solve in getting to production.

RISC-V intentionally contained almost no innovation of any kind. The whole point was to have the most boring, standard RISC design imaginable, without anything clever in it. That's what you want for introducing students to their first RISC architecture, and also as a basis for doing computer architecture or CPU fabrication research: on zero-overhead loops, compressed instruction sets, scalable vector instruction sets, IoT machine learning, indium gallium zinc oxide thin-film transistors printed on kapton, zero-knowledge virtual machines, or whatever.

They specifically wanted to avoid the kinds of "quirks" that vendors like Intel and ARM used to make people subject to their patents.

They did try to avoid what they saw as the blunders of past designs, like not leaving enough opcode space for compressed instructions, making instructions conditional, leaving out byte and halfword memory access instructions, having a flags register, having a complicated page table structure, having register windows, having delay slots, etc. None of that was innovative. The actual design of the compressed instruction set and the vector instruction set were innovative, but that came later.

> The Mill was the opposite extreme.

Sure, but even so they should have made real chips and iterated on silicon, not just simulations.

It’s the SpaceX rapid iteration development cycle vs NASA waterfall.

This could be wrong, but https://tracxn.com/d/companies/mill-computing/__5BCN3HKJOoke... says they raised US$100k in debt, and https://www.crunchbase.com/organization/mill-computing-inc says You Have Been Blocked but apparently told Google they were pre-seed funding. https://pitchbook.com/profiles/company/169749-55#funding claims that they raised US$3.2M (US$1.2M in angel funding in 02004 and US$2M in a seed round in 02016).

Even in 02016, I don't think US$2M was enough to tape out a silicon prototype of a working high-performance CPU. MPW ("shuttle") programs can give you working prototypes for as low as US$3000, but only in process nodes a decade or more behind the state of the art. US$30M is a much more plausible budget.

> leaving out byte and halfword memory access instructions

Huh? LB(U) / LH(U)

The Alpha left out byte and halfword memory access instructions, and ARM left out halfword access instructions; both had to correct the omission later. I said RISC-V was determined not to repeat "what they saw as the blunders of past designs", so it had those from the beginning.

Distance-based ISA, which is the essence of belt-machines, is currently subject of intense R&D in Japan, see e.g.:

https://www.sigarch.org/distance-based-isa-for-efficient-reg...

Ivan once was here on HN, I wonder how he's doing.